The present invention relates to a semiconductor integrated circuit including a nonvolatile memory cell array and particularly relates to an unstable bit detection method for the same.
A nonvolatile memory such as a flash memory holds information written therein even after an external power supply is shut down. Therefore, once information relating to control of another circuit or the like (e.g. flags) is written in a nonvolatile memory, the information written in the nonvolatile memory can be referred to, even if power supply to the circuit to be controlled is shut down, so that the circuit to be controlled can be easily returned to normal operation.
For example, an ECU (electronic control unit) is provided with a nonvolatile memory, and is arranged such that a value “AA” to indicate normal operation is set in the nonvolatile memory when the ECU operates, and the value is reset to “00” when the operation is completed. Then, if power supply shutdown occurs during operation of the ECU, the value in the nonvolatile memory remains at “AA”, and it can be known that the operation of the ECU has not been terminated normally when power is supplied to the ECU next time. Such a technique is described for example in Japanese Laid-Open Patent Publication No. H08-178976.
Additionally, when an operation such as write operation is performed on a flash memory, information to follow up this operation is written in a separate nonvolatile memory. This makes it possible to know, even if power supply to the flash memory is shut down, the state of the flash memory based on the follow-up information written in the nonvolatile memory once the power is turned on again. Thus, malfunction of a memory device with the flash memory can be prevented. Such a technique is described for example in Japanese Laid-Open Patent Publication NO. 2005-222202.